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[ak4708] ms0618-e-00 2007/04 - 1 - general description the ak4708 is an iic controlled audio and video switch matrix designed for digital tv and set-top-box applications. the ak4708 offers the i deal features for digital set-t op-box systems. the ak4708 includes the audio switches, video switches , video filters. the ak4708 provi des high performance audio and video routings to meet dual scart connections. the ak 4708 is supplied in a small 48-pin lqfp package to contribute space saving in pcb. features ? analog switches for scart audio section thd+n: ? 86db (@2vrms) dynamic range: 96db (@2vrms) analog inputs two full differential stereo inputs or single-ended input for decoder dac two stereo inputs (tv & vcr scart) analog outputs two stereo outputs (tv & vcr scart) stereo analog volume with pop-noise free circuit (+6db to ?60db & mute) pop noise free circuit for power on/off video section vcr scart supports rgb mode integrated lpf: ? 40db@27mhz 75 driver 6db gain for outputs four cvbs/y inputs (encx2, tv, vcr) , two cvbs/y outputs (tv, vcr) three r/c inputs (encx2, vcr), two r/c outputs (tv, vcr) two g and b inputs (enc, vcr), two g and b outputs (tv, vcr) tv/vcr input monitor loop-through mode for standby auto-startup mode for power saving scart pin#16 (fast blanking), pi n#8 (slow blanking) control ? power supply 5v+/ ? 5% and 12v+/ ? 10% small current consumption in standby mode (vd=10 a typ., vvd1+vvd2=10 a typ., vp=10 a typ.) ? package 48-pin lqfp av scart switch with two rgb outputs ak4708
[ak4708] ms0618-e-00 2007/04 - 2 - block diagram tvoutl tvoutr vcroutl vcroutr tvinl t vinr vcrinl vcrinr a inl+ a inl- a inr- a inr+ bias tv1-0 mono scl sda register control pdn pvcom vd vcr1-0 vmono dvcom vp amp vss -6db to +12db (3db/step) volume #0 +6 to -60db (2db/step) volume #1 audio block
[ak4708] ms0618-e-00 2007/04 - 3 - enc c tvrc enc g/cvbs vcr g tvg enc b/pb vcr b/pb tvb enc y tvvout 6db enc r/c/pr vcrvout vcrc vcr cvbs/y tv cvbs vcr r/c/pr enc cvbs/y encc encg vcrg encb vcrb enc y encrc vcrvin tvvin vcrrc enc v ( typical connection ) tv scar t vcr scart ( typical connection ) vvd2 vvss vvd1 monitor 6db 6db vcrgo vcrbo 6db 6db 6db 6db 6db video block
[ak4708] ms0618-e-00 2007/04 - 4 - monitor vcr fb tvfb 6db 0v 2v tvsb vcrsb 0/ 6/ 12v 0/ 6/ 12v vcrfb ( typical connection ) tv scar t vcr scart ( typical connection ) int 6db 0v 2v vcrfbo video blanking block
[ak4708] ms0618-e-00 2007/04 - 5 - ordering guide ak4708eq -10 +70 c 48pin lqfp (0.5mm pitch) AKD4708 evaluation board for ak4708 pin layout vd 37 vcrbo 36 38 ainr+ 39 ainl- 40 ainl+ 41 scl 42 43 sda 44 pdn 45 vcrgo 46 vcrfbo 47 vss 35 34 33 32 31 30 29 28 27 26 vcrc 1 vvss 2 tvvout 3 vvd2 4 tvrc 5 tvg 6 tvb 7 vvd1 8 encb 9 encg 10 encrc 11 23 22 21 20 19 18 17 16 15 14 13 tvvin ency encv top view vcrvout 48 encc 12 24 25 tvfb ainr- ak4708 vcrfb vcrvin vcrg vcrrc int vcrb vcrsb tvsb vcrinr tvoutl tvoutr vcroutl vcroutr tvinl tvinr vcrinl pvcom dvcom vp
[ak4708] ms0618-e-00 2007/04 - 6 - pin/function no. pin name i/o function 1 vcrc o chrominance output pin for vcr 2 vvss - video ground pin #1, 0v 3 tvvout o composite/luminance output pin for tv 4 vvd2 - video power supply pin #2, 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 5 tvrc o red/chrominance output pin for tv 6 tvg o green output pin for tv 7 tvb o blue output pin for tv 8 vvd1 - video power supply pin #1, 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 9 encb i blue input pin for encoder 10 encg i green input pin for encoder 11 encrc i red/chrominance input pin #1 for encoder 12 encc i chrominance input pin #2 for encoder 13 encv i composite/luminance input pin #1 for encoder 14 ency i composite/luminance input pin #2 for encoder 15 tvvin i composite/luminance input pin for tv 16 vcrvin i composite/luminance input pin for vcr 17 vcrfb i fast blanking input pin for vcr 18 vcrrc i red/chrominance input pin for vcr 19 vcrg i green input pin for vcr 20 vcrb i blue input pin for vcr 21 int o interrupt pin for video blanking normally connected to vd(5v) through 10k resistor externally. 22 vcrsb i/o slow blanking input/output pin for vcr 23 tvsb o slow blanking output pin for tv 24 vcrinr i rch vcr audio input pin 25 vcrinl i lch vcr audio input pin 26 tvinr i rch tv audio input pin 27 tvinl i lch tv audio input pin 28 vcroutr o rch analog output pin #1 29 vcroutl o lch analog output pin #1 30 tvoutr o rch anal og output pin #2 31 tvoutl o lch analog output pin #2 32 vp - power supply pin, 12v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 33 dvcom o audio common voltage pin #1 normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 34 pvcom o audio common voltage pin #2 normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. the caps affect the settling time of audio bias level. 35 vss - ground pin , 0v
[ak4708] ms0618-e-00 2007/04 - 7 - pin/function (continued) no. pin name i/o function 36 vd - power supply pin, 5v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 37 ainr ? i rch negative analog input pin 38 ainr+ i rch positive analog input pin 39 ainl ? i lch negative analog input pin 40 ainl+ i lch positive analog input pin 41 scl i control data clock pin 42 sda i/o control data pin 43 pdn i power-down mode pin when at ?l?, the ak4708 is in the power-down mode and is held in reset. the ak4708 should always be reset upon power-up. 44 vcrbo o blue output pin for vcr 45 vcrgo o green output pin for vcr 46 vcrfbo o fast blanking output pin for vcr 47 vcrvout o composite/luminance output pin for vcr 48 tvfb o fast blanking output pin for tv note: all digital input pins should not be left floating.
[ak4708] ms0618-e-00 2007/04 - 8 - internal equivalent circuit pin no. pin name type equivalent circuit description 41 43 scl pdn digital in vd 200 vss 38 37 39 40 ainr+ ainr ? ainl ? ainl+ audio in vd 150k vss 42 sda digital i/o vd vss 200 i2c bus voltage must not exceed vd. 21 int digital out v ss vvd1 normally connected to vd(5v) through 10k resister externally. 47 48 3 5 6 7 1 44 45 46 vcrvout tvfb tvvout tvrc tvg tvb vcrc vcrgo vcrbo vcrfbo video out vvd2 vvss1 vvd2 vvss2
[ak4708] ms0618-e-00 2007/04 - 9 - pin no. pin name type equivalent circuit description 9 10 11 12 13 14 15 16 17 18 19 20 encb encg encrc encc encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb video in vvd1 200 vvss (60k) the 60k is attached for chrominance input. 22 23 vcrsb tvsb video sb vp vvss vp vvss vvss 200 (120k) the 120k is not attached for tvsb. 24 25 26 27 vcrinr vcrinl tvinr tvinl audio in vp 150k vss 28 29 30 31 vcroutr vcroutl tvoutr tvoutl audio out vp vss vp vss 100 33 34 dvcom pvcom vcom out vd vss vd vss 100 vd vss
[ak4708] ms0618-e-00 2007/04 - 10 - absolute maximum ratings (vss =vvss = 0v;note 1) parameter symbol min max units power supply ( note 2) vd vvd1 vvd2 vp ? 0.3 ? 0.3 ? 0.3 ? 0.3 6.0 6.0 6.0 15 v v v v input current (any pins except for supplies) iin - 10 ma input voltage vind ? 0.3 vd+0.3 v video input voltage vinv ? 0.3 vvd1+0.3 v audio input voltage (except ainl+/ ? , ainr+/ ? pins) vina1 ? 0.3 vp+0.3 v audio input voltage (ainl+/ ? , ainr+/ ? pins) vina2 ? 0.3 vd+0.3 v ambient operating temperature ta ? 10 70 c storage temperature tstg ? 65 150 c note 1.all voltages with respect to ground. note 2.vss and vvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
[ak4708] ms0618-e-00 2007/04 - 11 - recommended operating conditions (vss = vvss = 0v; note 1) parameter symbol min typ max units power supply ( note 2) vd vvd1 vvd2 vp 4.75 4.75 4.75 10.8 5.0 5.0 5.0 12 5.25 5.25 vvd1 13.2 v v v v note 1. all voltages with respect to ground. note 2. vvd1 and vvd2 must be connected to the same voltage. *akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. electrical characteristics (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v) power supplies min typ max units power supply current normal operation (pdn = ?h?) ( note 3) vd+vvd1+vvd2 vp power-down mode (pdn = ?l?) ( note 4) vd vvd1+vvd2 vp 5 10 10 10 120 10 100 100 100 ma ma a a a note 3. stby bit = ?0?, all video outputs active. no signal, no load for a/v switches. note 4. all digital inputs are held at vd or vss. digital characteristics (ta = 25 c; vd = 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.0 - - - - 0.8 v v low-level output voltage (sda pin: iout= 3ma, int pin: iout= 1ma) vol - - 0.4 v input leakage current (except vcrsb pin) iin - - 10 a
[ak4708] ms0618-e-00 2007/04 - 12 - analog characteristics (audio) (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v; signal frequency = 1khz; measurement frequency = 20hz 20khz; r l 4.5k ; 0db=2vrms output; unless otherwise specified) parameter min typ max units analog input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage 2.0 vrms input resistance 100 150 - k analog input: (ainl+/ainl-/ainr-/ainr+ pins) analog input characteristics input voltage (ain+) ? (ain ? ) ( note 6) 2.0 vrms input resistance (ainl+, ainr+ pins) ( note 7) 140 210 k input resistance (ainl-, ainr- pins) ( note 7) 75 115 - k stereo/mono output: (tvoutl/tvoutr/vcroutl/vcrout r pins) ( note 5) analog output characteristics volume#0 step width ( note 8) 2.3 3.0 3.7 db volume#1 step width (+6db to ?12db) (-12db to ?40db) (-40db to ?60db) 1.6 0.5 0.1 2 2 2 2.4 3.5 3.9 db db db thd+n (at 2vrms output, note 9) ( at 3vrms output, note 9 , note 10) ? 86 -60 -80 db db dynamic range ( ? 60db output, a-weighted, note 9) 92 96 db s/n (a-weighted, note 9) 92 96 db interchannel isolation ( note 9, note 11) 80 90 db interchannel gain mismatch ( note 9, note 11) - 0.3 - db gain drift - 200 - ppm/ c load resistance (ac-lord) tvoutl/r, vcroutl/r 4.5 k load capacitance tvoutl/r, vcroutl/r 20 pf output voltage ( note 13) 1.85 2 2.15 vrms power supply rejection (psr) ( note 12) - 50 db note 5. measured by audio precision system two cascade. note 6. if input is single ended, maximum input voltage is 1vrms. note 7. differential signal is input to ain- and ain+. volume #0 = 0db. note 8. the output level of the internal amp with volume #0 should be less than 2vrms.. the output level must be adjust ed by the volume #1 when output level of the ak4708 exceeds 2vrms. note 9. analog in to tvout. path : ainl+/ ? tvoutl, ainr+/ ? tvoutr note 10. except vcroutl/vcroutr pins. note 11. between tvoutl and tvoutr with analog inputs ainl+/ ? , ainl/r+/ ? , 1khz/0db. note 12. the psr is applied to vd with 1khz, 100mv. note 13. the audio output mu st not exceed 3vrms at vp 5%. the audio output must not exceed 2.15vrms at vp 10%.
[ak4708] ms0618-e-00 2007/04 - 13 - analog characteristics (video) (ta = 25 c; vp = 12v, vd= 5v; vvd1 = vvd2 = 5v; unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.7 v r/g/b clamp voltage at output pin. 0.7 v pb/pr clamp voltage at output pin. 2.2 v chrominance bias voltage at output pin. 2.2 v gain input = 0.3vp-p, 100khz 5.5 6 6.5 db interchannel gain mismatch1 tvrc, tvg, tvb. input = 0.3vp-p, 100khz. -0.5 - 0.5 db interchannel gain mismatch2 vcrc, vcrgo, vcrbo. input = 0.3vp-p, 100khz. -0.5 - 0.5 db frequency response input=0.3vp-p, c1=c2=0pf. 100khz to 6mhz. at 10mhz. at 27mhz. -1.0 -3 -40 0.5 -25 db db db group delay distortion at 4.43mhz with respect to 1mhz. 15 ns input impedance chrominance input (internally biased) 40 60 - k input signal f = 100khz, maximum with distortion < 1.0%, gain = 6db. - - 1.5 vpp load resistance ( figure 1) 150 - - load capacitance c1 ( figure 1) c2 ( figure 1) 400 15 pf pf dynamic output signal f = 100khz, maximum with distortion < 1.0% - - 3 vpp y/c crosstalk f = 4.43mhz, 1vp-p input. among tvvout, tvrc and vcrvout outputs. - ? 50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw = 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.6 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.8 - degree video signal output 75 ohm 75 ohm max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
[ak4708] ms0618-e-00 2007/04 - 14 - switching characteristics (ta = 25 c; vp = 10.8 13.2v, vd = 4.75 5.25v, vvd1 = vvd2 = 4.75 5.25v) parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 14) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf reset timing pdn pulse width ( note 15) tpd 150 ns note 14. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 15. the ak4708 should be reset by pdn pin = ?l? upon power up. note 16. i 2 c is a registered trademark of philips semiconductors.
[ak4708] ms0618-e-00 2007/04 - 15 - timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 2. i 2 c bus mode timing tpd vil pdn figure 3. power-down timing
[ak4708] ms0618-e-00 2007/04 - 16 - operation overview 1. system reset and power-down options the ak4708 should be reset once by bringing pdn pin = ?l ? upon power-up. the ak4708 has several operation modes. the pdn pin, auto bit, bias bit, stby bit a nd amp bit control operation modes as shown in table 1 and table 2. mode pdn pin auto bit stby bit bias bit mode 0 ?l? x x x full power-down 1 ?h? 1 x x auto startup mode (power-on default) 2 ?h? 0 1 1 standby & mute 3 ?h? 0 1 0 standby 4 ?h? 0 0 1 mute (amp power down) 5 ?h? 0 0 0 normal operation (amp operation) table 1. operation mode settings (x: don?t care) mode register control audio bias level video output tvfb tvsb vcrfbo vcrsb 0 full power-down not available 1 no video input power down hi-z hi-z pull -down ( note 17) auto startup mode (power-on default) video input ( note 18) active active ( note 25) 2 standby & mute power down 3 standby active 4 mute (amp power down) power down 5 normal operation (amp operation) available active ( note 19) hi-z/ active active active note 17. internally pulled down by 120k (typ) resistor. note 18. video input to tvvin or vcrvin. note 19. tvoutl/r are muted by mute bit in the default state. note 20. vcrc, vcrgo, vcrbo output 0v for termination. table 2. status of each operation modes
[ak4708] ms0618-e-00 2007/04 - 17 - system reset and full power-down mode the ak4708 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: power down pin l: device power down & reset h: normal operation. auto startup mode after when the pdn pin is set to ?h?, the ak4708 is in the auto startup mode. in this mode, all blocks except for the video detection circuit are powered down. once the video detecti on circuit detects video signal from tvvin pin or vcrvin pin, the ak4708 goes to the stand-by mode automatically a nd sends ?h? pulse via int pin. the sources of tvoutl/r are fixed to vcrinl/r, the sources of vcroutl/r are fixed to tvinl/r resp ectively. the source of dc- restore circuit is vcrvin pin. to exit the auto startup mode, set the auto bit to ?0?. auto bit (00h d3): auto startup bit 0: auto startup disable. (manual startup) 1: auto startup enable. (default) bias mode when the bias bit = ?1?, the bias voltage on the audio output goes to gnd level. bringing bias bit to ?0? changes this bias voltage smoothly from gnd to vp/2 by 2sec (typ.). this removes the huge click noise re lated the sudden change of bias voltage at power-on. the change of bias bit from ?1? to ?0? also makes smooth transient from vp/2 to gnd by 2sec (typ). this removes the huge click noise related the sudden change of bias voltage at power-off. bias bit (00h d1): bias-off bit 0: normal operation. 1: set the audio bias to gnd. (default) standby mode when the auto bit = bias bit = ?0? and the stby bit = ?1?, the ak4708 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r pins are fixed to vcrinl/r pins; the sources of vcroutl/r are fixed to tvinl/r pins respectively. all register values themselves are not changed by stby bit = ?1?. stby bit (00h d0): standby bit 0: normal operation. 1: standby mode. (default)
[ak4708] ms0618-e-00 2007/04 - 18 - normal operation mode to change analog switches, set the auto bit, bias bit and stby bit to ?0?. the ak4708 is in power-down mode until pdn pin = ?h?. the figure 4 shows an example of the system timing at the power-down and power-up by pdn pin. typical operation sequence (auto setup mode) the figure 4 shows an example of the system timing at auto startup mode. a uto startup enable pdn pin a udio out (dc) tvvout, vcrvout active (loop-through) tvvin signal in no signal don?t care signal in no signal don?t care vcrvin signal in no signal don?t care don?t care active (loop-through) hi-z hi-z active (loop-through) (gnd) active (loop-through) no signal no signal hi-z low power mode low power mode low power mode a uto bit ?1?(defaoult) figure 4.auto startup mode sequence typical operation sequence (except auto setup mode) figure 5 shows an example of the system timing at normal operation mode. pdn p in ?1? (default) stby bit ?0? ?1? ?1? (default) bias bit ?0? ?stand-by? ?1? ?0? ?stand-by? ?mute? tv out amp tv-source select vcr in vcr in vcr in (note 21) vcr in fixed to vcr in(loop-through) (default) ?1? (default) a uto bit ?0? amp amp fixed to vcr in(loop-through) ?1? (note 22) note 21. set the stby bit = ?0? to pass for 20.2ms after set the vmute bit = ?0?, to prevent the click noise. note 22. mute the analog outputs externally if click noise affects the system. figure 5. typical operating sequence
[ak4708] ms0618-e-00 2007/04 - 19 - 2. audio block switch control the ak4708 has switch matrixes designed primarily for scart routing. those are controlled via the control register as shown in, table 3 and table 4 (please refer to the block diagram). (01h: d1-d0) tv1 tv0 source of tvoutl/r 0 0 amp 0 1 vcrin (default) 1 0 mute 1 1 (reserved) table 3. tvout switch configuration (01h: d5-d4) vcr1 vcr0 source of vcroutl/r 0 0 amp 0 1 tvin (default) 1 0 mute 1 1 volume#1 output table 4. vcrout switch configuration volume control #0 (7-level volume) the ak4708 has a 7-level volume control (volume #0) as shown in table 5. the volume reflects the change of register value immediately. figure 6. volume #0(volume gain=0db:default), full differential stereo input (0dh: d5-d3) vol2 vol1 vol 0 volume #0 gain output level (typ) 1 1 1 +12db 2vrms (with 0.5vrms differential input) 1 1 0 +9db - 1 0 1 +6db 2vrms (with 1vrms differential input) 1 0 0 +3db - 0 1 1 0db 2vrms (with 2vrms differential input) (default) 0 1 0 -3db - 0 0 1 -6db 1vrms (with 2vrms differential input) 0 0 0 mute - note: volume #1=0db table 5. volume #0, full differential stereo input 2vrms differential input tvoutl/r (vcroutl/r) a inl/r+ a inl/r- volume gain 0db volume #0 1vrms 1vrms 2vrms 0.47 0.47
[ak4708] ms0618-e-00 2007/04 - 20 - figure 7. volume #0(volume gain=0db:default), single-ended input (0dh: d5-d3) vol2 vol 1 vol 0 volume #0 gain output level (typ) 1 1 1 +12db 2vrms (with 0.5vrms input) 1 1 0 +9db - 1 0 1 +6db 2vrms (with 1vrms input) 1 0 0 +3db - 0 1 1 0db 1vrms (with 1vrms input) (default) 0 1 0 -3db - 0 0 1 -6db 0.5vrms (with 1vrms input) 0 0 0 mute - note: volume #1=0db table 6. volume #0, single-ended input volume control #1 (main volume) the ak4708 has main volume control (volume #1) as shown in table 7. (02h: d5-d0) l5 l4 l3 l2 l1 l0 gain 1 0 0 0 1 0 +6db 1 0 0 0 0 1 +4db 1 0 0 0 0 0 +2db 0 1 1 1 1 1 0db (default) ? ? ? ? ? ? ? 0 0 0 0 0 1 -60db 0 0 0 0 0 0 mute note: the output must not exceed 3vrms. table 7. volume #1 when the mod bit = ?1?(default), changing levels don?t ha ve pop noise. mdt1-0 bits select the transition time ( table 8). when the new gain value 1eh(-2db) is written to gain resistor while the actual (stable) gain is 1fh(0db), the gain changes to 1eh(-2db) within the transition time selected by mdt1-0 bits. the ak4708 compares the actual gain to the value of gain register after finishing the transition time, and re-changes the actual gain to new resister value within the transition time if the register value is different from the act ual gain when compared. when the mod bit = ?0 ? then there is no transition time and the gain changes immediately. this change may cause a click noise. a inl/r+ a inl/r- tvoutl/r (vcroutl/r) volume gain 0db volume #0 1vrms 1vrms 0.47 0.47
[ak4708] ms0618-e-00 2007/04 - 21 - a ctual gain gain register transition time (5.3ms to 42.7ms pop free.) 1fh 1eh 1dh 1eh 1fh 1dh wr [gain=1eh] wr [gain=1ch] wr [gain=1dh] 1ch 1ch compare compare compare (to 1eh) (to 1dh) (to 1ch) figure 8. volume change operation (mod bit = ?1?) mdt1 mdt0 transition time 0 0 5.3ms 0 1 10.7ms 1 0 21.3ms 1 1 42.7ms (default) table 8. volume transition time (typ.)
[ak4708] ms0618-e-00 2007/04 - 22 - 3. video block video switch control the ak4708 has switches for tv and vcr. each switch can be controlled via registers independently. when auto bit = ?1? or stby bit = ?1?, these switches setting is ignored a nd set to fixed configuration (loop-through mode). please refer the auto startup mode and standby mode. (04h: d2-d0) mode vtv2-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs+rgb or encoder ypbpr 001 encv pin (encoder cvbs or y) encrc pin (encoder red,c or pb) encg pin (encoder green or y) encb pin (encoder blue or pr) encoder y/c 1 010 encv pin (encoder y) encrc pin (encoder c) (hi-z) (hi-z) encoder y/c 2 011 ency pin (encoder y) encc pin (encoder c) (hi-z) (hi-z) vcr (default) 100 vcrvin pin (vcr cvbs or y) vcrrc pin (vcr red,c or pb) vcrg pin (vcr green or y) vcrb pin (vcr blue or pr) tv cvbs 101 tvvin pin (tv cvbs) (hi-z) (hi-z) (hi-z) (reserved) 110 - - - - (reserved) 111 - - - - table 9. tv video output ( note 23) (04h: d5-d3) mode vvcr2-0 bit source of vcrvout pin source of vcrc pin source of vcrgo pin source of vcrbo pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs or y/c 1 001 encv pin (encoder cvbs or y) encrc pin (encoder c) (hi-z) (hi-z) encoder cvbs or y/c 2 010 ency pin (encoder cvbs or y) encc pin (encoder c) (hi-z) (hi-z) tv cvbs (default) 011 tvvin pin (tv cvbs) (hi-z) (hi-z) (hi-z) vcr 100 vcrvin pin (vcr cvbs) vcrrc pin (vcr red, c) vcrg pin (vcr green) vcrb pin (vcr blue) encoder cvbs /rgb 101 encv pin (encoder cvbs or y) encrc pin (encoder red,c or pb) encg pin (encoder green or y) encb pin (encoder blue or pr) (reserved) 110 - - - - (reserved) 111 - - - - table 10. vcr video output (refer note 23) note 23. when input the video si gnal via encrc pin or vcrrc pin, se t clamp1-0 bits respectively.
[ak4708] ms0618-e-00 2007/04 - 23 - video output control (05h: d6-d0, 0ch:d2-d0) each video output can be set to hi-z individually via contro l registers. these settings are ignored when the auto bit = ?1?. tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control vcrg: vcrgo output control vcrb: vcrbo output control tvfb: tvfb output control vcrfb: vcrfbo output control 0: hi-z. (default) 1: active. rgb/chroma bi-directional control for vcr scart (05h: d7, d5) the ak4708 supports the bi-directional rgb/chroma signal on the vcr scart. (ak4708) vcrrc pin vcrc pin vcr scart 75 0.1u (cio bit & vcrc bit) #15 pin figure 9. vcr red/chroma bi-directional control cio vcrc state of vcrc pin 0 0 hi-z (default ) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 11 vcr red/chroma bi-directional control
[ak4708] ms0618-e-00 2007/04 - 24 - (ak4708) vcrg pin vcrgo pin vcr scart 75 0.1u (cio bit & vcrg bit) #11 pin figure 10. vcr green bi-directional control cio vcrg state of vcrgo pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 12 vcr green bi-directional control (ak4708) vcrb pin vcrbo pin vcr scart 75 0.1u (cio bit & vcrb bit) #7 pin figure 11. vcr blue bi-directional control cio vcrb state of vcrc pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 13 vcr blue bi-directional control
[ak4708] ms0618-e-00 2007/04 - 25 - clamp and dc-restore circuit control (06h: d7-d2) each cvbs and y input has the sync tip clamp circuit. the dc-restore circuit has two clamp voltages 0.7v(typ) and 2.2v(typ) to support both rgb and ypbpr signal. they correspond to 0.35v(typ) and 1.1v(typ) at the scart connector when matched by 75 resistors. the clamp1, clam p0 and clampb bits select the input circuit for encrc pin (encoder red/chroma), encb pin (encoder blue), vcrrc pin (vcr red/chroma) and vcrb pin (vcr blue) respectively. vclp2-0 bits select the sync source of dc- restore circuit. clampb clamp0 vcrrc input circuit vcrb input circuit note 0 0 dc restore clamp active (0.7v at sync timing/output pin) dc restore clamp active (0.7v at sync timing/output pin) for rgb 0 1 biased (2.2v at sync timing/output pin) (dc restore clamp active) (0.7v at sync timing output pin) for y/c (default) 1 0 dc restore clamp active (2.2v at sync timing/output pin) dc restore clamp active (2.2v at sync timing/output pin) for y/pb/pr 1 1 (reserved) (reserved) table 14. dc-restore control for vcr input clampb clamp1 encrc input circ uit encb input circuit note 0 0 dc restore clamp active (0.7v at sync timing/output pin) dc restore clamp active (0.7v at sync timing/output pin) for rgb (default) 0 1 biased (2.2v at sync timing/output pin) dc restore clamp active (0.7v at sync timing output pin) for y/c 1 0 dc restore clamp active (2.2v at sync timing/output pin) dc restore clamp active (2.2v at sync timing/output pin) for y/pb/pr 1 1 (reserved) (reserved) table 15. dc-restore control for encoder input clamp2 encg input circuit note 0 dc restore clamp active (0.7v at sync timing/output pin) for rgb (default) 1 sync tip clamp active (0.7v at sync timing/output pin) for y/pb/pr note: when the vtv2-0 bits = ?001?(source for tv = encoder cvbs /rgb), tvg bit = ?1? (tvg = active) and vclp1-0 bits = ?11?(dc restore source = encg), the sync tip is selected even if the clamp2 bit = ?0?. table 16. dc-restore control for encoder green/y input vclp2-0: dc restore source control vclp2 vclp1 vclp0 sync source of dc restore 0 0 0 encv (default) 0 0 1 ency 0 1 0 vcrvin 0 1 1 encg 1 0 0 vcrg 1 0 1 (reserved) 1 1 0 (reserved) 1 1 1 (reserved) note: when the auto bit = ?1?, the source is fixed to vcrvin. table 17. dc-restore source control
[ak4708] ms0618-e-00 2007/04 - 26 - 4. blanking control the ak4708 supports fast blanking signals and slow bl anking (function switching) signals for tv/vcr scart. input/output control for fast/slow blanking fb1-0: tv fast blanking output control (07h: d1-d0) fb1 bit fb0 bit tvfb pin output level 0 0 0v (default) 0 1 2v<, 4v(typ) at 150 load 1 0 same as vcr fb input (4v/0v) 1 1 (reserved) table 18. tv fast blanking output (note: minimum load is 150 ) sbt1-0: tv slow blanking output control (07h: d3-d2) sbt1 bit sbt0 bit tvsb pin output level 0 0 < 2v (default) 0 1 5v <, < 7v 1 0 (reserved) 1 1 10v < table 19. tv slow blanking output (note: minimum load is 10k ) fbv: vcr fast blanking output control (0ch: d7) fbv bit vcrfbo pin output level 0 0v (default) 1 2v<, 4v(typ) at 150 load table 20. vcr fast blanking output (note: minimum load is 150 ) sbv1-0: vcr slow blanking output control (07h: d5-d4) sbv1 bit sbv0 bit vcrsb pin output level 0 0 < 2v (default) 0 1 5v <, < 7v 1 0 (reserved) 1 1 10v < table 21. vcr slow blanking output (note: minimum load is 10k ) sbio1-0: tv/vcr slow blanking i/o control (07h: d7-d6) sbio1 bit sbio0 bit vcrsb pin direction tvsb pin direction 0 0 output (controlled by sbv1-0 bits) output (controlled by sbt1-0 bits) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1-0 bits) output (controlled by sbt1-0 bits) 1 1 input (stored in svcr1-0 bits) output (same output as vcr sb) table 22. tv/vcr slow blanking i/o control
[ak4708] ms0618-e-00 2007/04 - 27 - vcr fast blanking for vcr scart (0ch: d7, d2) the ak4708 supports the bi-directional vcr fast blanking signal on the vcr scart. (ak4708) vcrfb pin vcrfbo pin vcr scart 75 (vcrfb bit) #16 pin 6db 0v 2v (fbv bit) figure 12. vcr fast blanking bi-directional control fbv vcrfb state of vcrfbo pin 0 0 hi-z (default) 0 1 active / 0v(typ) 1 0 hi-z 1 1 active / 2v<, 4v(typ) at 150 load table 23 vcr fast blanking bi-directional control
[ak4708] ms0618-e-00 2007/04 - 28 - 5. monitor options and int function monitor options (08h: d4-d0) the ak4708 has several detection functions. svcr1-0 bits, fvcr bit, vcmon bit and tvmon bit reflect the input dc level of vcr slow blanking, the input dc level of vcr fast blanking and signals input to tvvin or vcrvin pins. svcr1-0: vcr slow blanking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 bits hold previous value. vcrsb pin input level svcr1 bit svcr0 bit < 2v 0 0 4.5 to 7v 0 1 (reserved) 1 0 9.5 < 1 1 table 24. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr bit < 0.4v 0 1v < 1 table 25. vcr fast blanking monitor (typical threshold is 0.7v) vcmon: vcrvin pin video input monitor (mcomn bit = ?1?), tvvin pin or vcrvin pin video input monitor (mcomn bit = ?0?) 0: no video signal detected. 1: detects video signal. tvmon: tvvin pin video input monitor (active when mcomn bit = ?1?) 0: no video signal detected. 1: detects video signal. auto (00h d3) mcomn (09h d7) tvvin signal vcrvin signal tvmon (08h d4) vcmon (08h d3) 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 1 x 0 0 0 0 1 x 0 1 0 1 1 x 1 0 0 1 1 x 1 1 0 1 x:don?t care note 24. tvvin/vcrvin signal: signal 0 = no signal applied, signal 1 = signal applied table 26. tv/vcr monitor function
[ak4708] ms0618-e-00 2007/04 - 29 - int function and mask options (09h: d3-d1) changes of the 08h status can be monitored via the int pin. the int pin is the open drain output and goes ?l? for 2 s (typ.) when the status of 08h is changed. this pin should be connected to vd (typ. 5v) through 10k resistor or lower voltage through 10k resistor. mtv bit, mvc bit, mcomn bit, mfvcr bit and msvcr bit control the reflection of the status change of these monitors onto the int pi n from report to prevent to masks each monitor. ak4708 r=10k ? int 5v up figure 13. int pin mvc: vcmon mask. refer table 28. mtv: tvmon mask. refer table 27. mcomn: refer table 26 auto (00h d3) tvmon (08h d4) mtv (09h d4) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z note 25. when the stby bit = ?0?, the tv monitor mask function is enabled. note 26. when auto bit = ?1?, tvmon does not change table 27. tv monitor mask auto (00h d3) vcmon (08h d3) mvc (09h d3) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z 1 change 0 generates ?l? pulse 1 change 1 generates ?l? pulse note 27. when the stby bit = ?0?, the vcr monitor mask function is enabled. table 28. vcr monitor mask mfvcr: fvcr monitor mask. 0: change of fvcr is reflected to int pin. (default) 1: change of fvcr is not reflected to int pin. msvcr: svcr1-0 monitor mask 0: change of svcr1-0 is reflected to int pin. (default) 1: change of svcr1-0 is not reflected to int pin.
[ak4708] ms0618-e-00 2007/04 - 30 - 6. control interface i 2 c-bus control mode 1. write operations figure 14 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 20). after the start condition, a slave address is sent. this address is 7bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the ak4708, the ak4708 generates the acknowledge and the opera tion is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 22). a ?1? for r/w bit indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the ak4708. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 16). the data after the second byte contain control data. the format is msb first, 8bits ( figure 17). the ak4708 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 20). the ak4708 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the ak4708 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after the receipt of each data, the internal address counter is incremented by one, and the ne xt data is taken into next address au tomatically. if the address exceeds 0dh prior to generating the stop condition, the addr ess counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 22) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 14. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 15. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 16. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 17. byte structure after the second byte
[ak4708] ms0618-e-00 2007/04 - 31 - 2. read operations set r/w bit = ?1? for read operations. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of termin ating the write cycle after the receipt th e first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop conditi on, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4708 supports two basic read operati ons: current address read and random read. 2-1. current address read the ak4708 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4708 generates an acknowledge, transmits 1byte data which address is set by the in ternal address counter and increments the internal address counter by 1. if the master does not ge nerate an acknowledge to the data but generate the stop condition, the ak4708 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 18. current address read 2-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the ak4708 generates an acknowledge, 1-byte data and increments the internal addr ess counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the ak4708 disc ontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 19. random address read
[ak4708] ms0618-e-00 2007/04 - 32 - scl sda stop condition start condition s p figure 20. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 21. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 22. bit transfer on the i 2 c-bus
[ak4708] ms0618-e-00 2007/04 - 33 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto 0 bias stby 01h switch vmute 0 vcr1 vcr0 mono 1 tv1 tv0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 03h zerocross 0 vmono 1 0 0 mod mdt1 mdt0 04h video switch 0 0 vvcr2 vv cr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable cio tvfb vcrc vcrv tvb tvg tvr tvv 06h video volume/clamp clampb vclp 1 vclp0 clamp2 clamp1 clamp0 0 0 07h s/f blanking control sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 fvcr1 tvmon vcmon fvcr0 svcr1 svcr0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 0ah dc restore 0 0 0 0 vclp2 0 1 1 0bh reserve 0 0 0 0 0 0 0 0 0ch vcr output fvb 0 0 0 0 vcrfb vcrb vcrg 0dh volume 0 0 vol2 vol1 vol0 1 1 1 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin = ?h?, all registers can be accessed. do not write any data to the register over 0dh. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto 0 bias stby r/w r/w default 0 0 0 0 1 0 1 1 stby: standby control 0: normal operation 1: standby mode (default). a ll registers are not initialized. amp: powered down and timings are reset. source of tvout: fixed to vcrin. source of vcrout: fixed to tvin. source of monoout: fixed to vcrin. source of tvvout: fixed to vcrvin (or hi-z). source of tvrc: fixed to vcrrc (or hi-z). source of tvg: fixed to vcrg (or hi-z). source of tvb: fixed to vcrb (or hi-z). source of vcrvout: fixed to tvvin (or hi-z). source of vcrc: fixed to hi-z. source of vcrgo: fixed to hi-z. source of vcrbo: fixed to hi-z. bias: audio output control 0: normal operation 1: all audio outputs to gnd (default) auto: auto startup bit 0: auto startup disable (manual startup). 1: auto startup enable (default). note: when the sbio1 bit = ?1?(defa ult = ?0?), the change of auto bit may cause a ?l? pulse on int pin.
[ak4708] ms0618-e-00 2007/04 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch vmute 0 vcr1 vcr0 mono 1 tv1 tv0 r/w r/w default 1 0 0 1 0 1 0 1 tv1-0: tvoutl/r pins source switch 00: amp 01: vcrinl/r pins (default) 10: mute 11: reserved mono: mono select for tvoutl/r pins 0: stereo. (default) 1: mono. (l+r)/2 vcr1-0: vcroutl/r pins source switch 00: amp 01: tvinl/r pins (default) 10: mute 11: volume#1 output vmute: mute switch for volume #1 0: normal operation 1: mute the volume #1 (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h main volume 0 0 l5 l4 l3 l2 l1 l0 r/w r/w default 0 0 0 1 1 1 1 1 l5-0: volume #1 control those registers control both lch and rch of volume #1. 111111 to 100011: (reserved) 100010: volume gain = +6db 100001: volume gain = +4db 100000: volume gain = +2db 011111: volume gain = +0db (default) 011110: volume gain = -2db ... 000011: volume gain = -56db 000010: volume gain = -58db 000001: volume gain = -60db 000000: volume gain = mute
[ak4708] ms0618-e-00 2007/04 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h volume control 0 vmono 1 0 0 mod mdt1 mdt0 r/w r/w default 0 0 1 0 0 1 1 1 mdt1-0: the time length control of volume transition time 00: typ. 5.3 ms 01: typ. 10.7 ms 10: typ. 21.3 ms 11: typ. 42.7 ms (default) mod: soft transition enable for volume #1 control 0: disable the volume value changes imme diately without soft transition. 1: enable (default) the volume value changes with soft transition. this function is disabled when stby bit = ?1?. vmono: mono select for vcroutl/r pins 0: stereo. (default) 1: mono. (l+r)/2
[ak4708] ms0618-e-00 2007/04 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch 0 0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 0 0 0 1 1 1 0 0 vtv2-0: selector for tv video output refer table 9. vvcr2-0: selector for vcr video output refer table 10. addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable cio tvfb vcrc vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control tvfb: tvfb output control 0: hi-z (default) 1: active. cio: vcr rgb i/o control for vcr scart refer table 11, table 12 and table 13.
[ak4708] ms0618-e-00 2007/04 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume clampb vclp1 vclp0 clamp2 clamp1 clamp0 0 0 r/w r/w default 0 0 0 0 0 1 0 0 clampb, clamp2-0: clamp control. refer table 14, table 15 and table 16. vclp1-0: dc restore source control 00: encv pin (default) 01: ency pin 10: vcrvin pin 11: (reserved) when the auto bit = ?1?, the s ource is fixed to vcrvin pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sb v1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking output control (for tvfb pin) 00: 0v (default) 01: 2v<, 4v(typ) at 150 load 10: follow vcr fb input (4v/0v) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pin. minimum load is 10k .) 00: < 2v (default) 01: 5v <, < 7v 10: (reserved) 11: 10v < sbv1-0: vcr slow blanking output control (for vcrsb pin. minimum load is 10k .) 00: < 2v (default) 01: 5v <, < 7v 10: (reserved) 11: 10v < sbio1-0: tv/vcr slow blanking i/o control refer table 22. addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h monitor 0 0 fvcr1 tvmon vcmon fvcr0 svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0, fvcr1-0: vcr fast blanking/slow blanking monitor refer table 24, table 25. vcmon, tvmon: vcr/tv video input monitor refer table 26.
[ak4708] ms0618-e-00 2007/04 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 r/w r/w default 0 0 0 0 1 0 0 0 msvcr: svcr1-0 bits monitor mask 0: the int pin reflects the cha nge of svcr1-0 bit. (default) 1: the int pin does not reflect the change of svcr1-0 bits. mfvcr: fvcr monitor mask 0: the int pin reflects the cha nge of mfvcr bit. (default) 1: the int pin does not reflect the change of mfvcr bit. mvc: vcr input monitor mask refer table 28. mtv: tv input monitor mask refer table 27. mcomn: monitor mask option refer table 26 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah dc restore 0 0 0 0 vclp2 0 1 1 r/w r/w default 0 0 0 0 0 0 1 1 vclp2: dc restore source control refer table 17 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch vcr output fbv 0 0 0 0 vcrfb vcrb vcrg r/w r/w default 0 0 0 0 0 0 0 0 vcrg: vcrgo output control vcrb: vcrbo output control vcrfb: vcrfbo output control 0: hi-z (default) 1: active. fbv: vcr fast blanking output control (for vcrfbo pin) 0: 0v (default) 0: 2v<, 4v(typ) at 150 load
[ak4708] ms0618-e-00 2007/04 - 39 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh main volume 0 0 vol2 vol1 vol0 1 1 1 r/w r/w default 0 0 0 1 1 1 1 1 vol2-0: volume #0 control those registers control both lch and rch of volume #0. 111: volume gain = +12db 110: volume gain = +9db 101: volume gain = +6db 100: volume gain = +3db 011: volume gain = +0db (default) 010: volume gain = -3db 001: volume gain = -6db 000: mute
[ak4708] ms0618-e-00 2007/04 - 40 - system design figure 23 shows the system connection diagram example. the evaluation board AKD4708 demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. tvfb 1 vvd1 2 vvss 3 tvvout 4vvd2 5 tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout pdn sd a scl ainl+ ainl- ainr+ ainr- 13 14 15 16 17 18 19 20 21 22 23 a k4708eq encrc 12 encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb int vcrsb tvsb vcrinr 24 35 34 33 32 31 30 29 28 27 26 25 36 dvcom vp vcroutl vcroutr tvinl tvoutl tvoutr tvinr vcrinl pvcom 48 47 46 45 44 43 42 41 40 39 38 37 encc 75 75 75 video 5v 0.1u 0.1u 0.1u 0.1u video encoder 0.1u 75 10u 0.1u + + mpeg micro controller 10u 0.1u a udio 5v 0.47u 0.47u 0.47u 0.47u decoder dacl dacr 75 75 + + a nalog 12v + 10u + 10u 220k + 10u + 10u tv scart 220k 220k 220k 300 300 300 300 0.47u 300 0.47u 300 0.47u 300 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u vcr scart 300 0.47u 400 400 75 75 75 75 10u 10u 0.1u 75 75 75 75 a nalog ground digital ground + vss vd 10u 10u 0.1u 0.1u 0.1u vcrc 75 75 75 75 vcrfbo vcrgo vcrbo + figure 23. typical connection diagram
[ak4708] ms0618-e-00 2007/04 - 41 - grounding and power supply decoupling vd, vp, vvd1, vvd2, vss and vvss should be supplied fro m analog supply unit with low impedance and be separated from system digital supply. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these pins to eliminate th e effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as near to vd (vp, vvd1, vvd2) as possible. voltage reference each dvcom/pvcom are common voltage of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these vcom pins to eliminat e the effects of high frequency noise. no load current should be drawn from these vcom pins. all signals, especially clocks , should be kept away from these vcom pins in order to avoid unwanted coupling into the ak4708. analog audio outputs the analog outputs are also single-ended and centered on 5.6v(typ.). the output signal range is typically 2vrms .
[ak4708] ms0618-e-00 2007/04 - 42 - external circuit example analog audio input pin tvinl/r vcrinl/r 0.47 f 300 (cable) analog audio input pin a inr+ a inr- a inl+ a inl- 0.47 f analog audio output pin tvoutl/r vcroutl/r 10 f 300 total > 4.5k (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb 0.1 f 75 (cable) 75 analog video output pin tvvout, tvrc tvg, tvr, tvb, vcrvout,vcrc, vcrbo,vcrgo max 400pf 75 75 max 15pf (cable)
[ak4708] ms0618-e-00 2007/04 - 43 - slow blanking pin tvsb vcrsb max 3nf (with 400 ) 400 (max 500 ) min: 10k (cable) fast blanking input pin vcrfb 75 (cable) 75 fast blanking output pin tvfb, vcrfbo 75 75 (cable)
[ak4708] ms0618-e-00 2007/04 - 44 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.145 0.05 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.5 0.2 0.5 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
[ak4708] ms0618-e-00 2007/04 - 45 - marking ak4708eq xxxxxxx 1 xxxxxxxx: date code identifier revision history date (yy/mm/dd) revision reason page contents 07/04/25 00 first edition
[ak4708] ms0618-e-00 2007/04 - 46 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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